The present invention relates to a semiconductor memory circuit device, particularly a technique effective in its application to a DRAM (Dynamic Random Access Memory).
A memory cell for holding 1 bit of information in a DRAM is constituted by a series circuit comprising a memory cell selecting MISFET and an information storing capacitor. A gate electrode in the memory cell selecting MISFET is connected to a word line extending in a row direction. One (or first) semiconductor region of the memory cell selecting MISFET is connected to one of complementary data lines which are formed for a first metallic wiring layer, while the other (or second) semiconductor region is connected to one (or first) electrode of the information storing capacitor. To the other (second) electrode of the information storing capacitor is applied a predetermined fixed potential. A word line is composed of two layers which are the gate electrode of the memory cell selecting MISFET and a second metallic wiring layer.
This type of a DRAM tends to be increased in its integration density for attaining a larger bit storage capacity and reduced in the size of each memory cell. When the memory cell size is reduced, the size of the information storing capacitor is also reduced, so that the amount of an electric charge which serves as information is also decreased. This decrease in the amount of an electric charge stored causes deterioration of the .alpha.-ray soft error resistance. In particular, in a DRAM of 1M bits or larger capacity, the improvement of the .alpha.-ray soft error resistance is one of important technical subjects.
Along such technical subject, there is now a tendency towards adoption of a stacked structure (STC structure) for the information storing capacitor of each memory cell in a DRAM. The information storing capacitor is constituted by laminating a lower (or first) electrode layer, a dielectric film and an upper electrode layer successively in this order on a semiconductor substrate. The lower (or first) electrode layer is connected to the other (or second) semiconductor region of the memory cell selecting MISFET and is extended up to above the gate electrode. The lower electrode layer is patterned to have a predetermined plane shape by the application of a photolithographic technique and an etching technique to a polycrystalline silicon film deposited according to a CVD method. The dielectric film is provided along upper and side faces of the lower electrode layer. The upper (second) electrode layer is provided on the surface of the dielectric films and it is constituted integrally with the upper electrode layer of the information storing capacitor of a stacked structure in other memory cells adjacent thereto and is used as a common plate electrode. Like the lower electrode layer, the upper electrode layer is formed using a polycrystalline silicon film.
In order to attain a higher integration density and a larger bit storage capacity in the DRAM of such a stacked structure there has been developed a technique of forming the lower electrode layer in a fin shape, or extending the lower electrode layer vertically upwards, or using the side faces (surfaces) of the lower electrode layers positively as a capacitance portion. Such DRAM is shown, for example, in U.S. Pat. No. 4,742,018 or IEDM 88, pages 592-595.